TFF ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_SRFF_vlog;

// Inputs
reg s;
reg r; reg clr;
reg pr;
reg clk;

// Outputs
wire q;
wire nq;

// Instantiate the Unit Under Test (UUT)
TFF_vlog uut (
.s(s),
.r(r), .clr(clr),
.pr(pr),
.clk(clk),
.q(q),
.nq(nq)
);

initial begin
forever begin
 clk=0;
 #50
 clk=1;
 #50
 clk=0;
 end
end

initial begin
s= 0; r= 0; clr = 0; pr = 0; #100;
clr = 0; pr = 1; #100;
clr = 1; pr = 0; #100;
clr = 1; pr = 1; #100;
#100;
s= 0; r= 1; #100;
s= 1; r= 0; #100; s= 1; r= 1; #100;
end
 
endmodule


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Program for TFF (  VERILOG  ) :-

module SRFF_vlog (input s ,input r ,input clr ,
input pr ,input clk , output q , output nq );
reg q;reg nq;
always @ (posedge clk) begin
 if (pr==0) begin
  q = 1;
  nq = 0;
 end else if (clr==0) begin
  nq = 1;
  q = 0;
 end else if (s!=r) begin
  q = s;
  nq = !s;
 end else if (s==0) begin
  q = q;
  nq = nq;
 end else begin
  q = x;
  nq = x;
 end
end

endmodule