Comparator Behavioral ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_Comparator_vlog;

// Inputs
reg [3:0] a;
reg [3:0] b;

// Outputs
wire equal;
wire greater;
wire lower;

// Instantiate the Unit Under Test (UUT)
comparator_vlog uut (
.a(a),
.b(b),
.equal(equal),
.greater(greater),
.lower(lower)
);

initial begin
// Initialize Inputs
a = 0; b = 0; #100;
a = 2; b = 5; #100;
a = 10; b = 4; #100;
a = 5; b = 14; #100;
a = 9; b = 8; #100;
       
// Add stimulus here

end
     
endmodule


--------------------------------------------------------------------------------------------------------------------------

Program for Comparator (  VERILOG  ) :-
module comparator_vlog ( a ,b ,equal ,greater ,lower );

output equal ;
reg equal ;
output greater ;
reg greater ;
output lower ;
reg lower ;

input [3:0] a ;
input [3:0] b ;

always @ (a or b) begin
 if (a<b) begin
  equal = 0;
  lower = 1;
  greater = 0;
 end else if (a==b) begin
  equal = 1;
  lower = 0;
  greater = 0;
 end else begin
  equal = 0;
  lower = 0;
  greater = 1;
 end
end


endmodule