Full Adder ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_FA_vlog;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)
FA_vlog uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0; b = 0; c = 0; #100;
a = 0; b = 0; c = 1; #100;
a = 0; b = 1; c = 0; #100;
a = 0; b = 1; c = 1; #100;
a = 1; b = 0; c = 0; #100;
a = 1; b = 0; c = 1; #100;
a = 1; b = 1; c = 0; #100;
a = 1; b = 1; c = 1; #100;
     
// Add stimulus here

end
   
endmodule

--------------------------------------------------------------------------------------------------------------------------

Program for FULL ADDER (  VERILOG  ) :-

module FA_vlog( input a,
      input b,input c,
      output sum,
      output carry );

assign sum = a ^ b ^ c;
assign carry = (a & b) | ((a ^ b) & c);
endmodule