3-Bit UP / DOWN Counter ( Behavioral ) with Test Bench Program

Test Bench Program :-

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_updown_3bit_beh IS

END tb_updown_3bit_beh;

ARCHITECTURE behavior OF tb_updown_3bit_beh IS

    COMPONENT updown_3bit_beh

    PORT(

         m : IN  std_logic;

         clk : IN  std_logic;

         pr : IN  std_logic;

         clr : IN  std_logic;

         q : OUT  std_logic_vector(2 downto 0)

        );

    END COMPONENT;

           

   signal m : std_logic := '0';

   signal clk : std_logic := '0';

   signal pr : std_logic := '0';

   signal clr : std_logic := '0';

   signal q : std_logic_vector(2 downto 0);

   constant clk_period : time := 10 ns;

BEGIN

   uut: updown_3bit_beh PORT MAP (

          m => m,

          clk => clk,

          pr => pr,

          clr => clr,

          q => q

        );

   clk_process :process

   begin

                   clk <= '0';

                   wait for clk_period/2;

                   clk <= '1';

                   wait for clk_period/2;

   end process;

   stim_proc: process

   begin                

          wait for clk_period;

                   pr<='1';clr<='1';

                   wait for clk_period*8;

                   m<='1';

                   wait for clk_period*5;

                   m<='0';

      wait;

      wait;

   end process;

END;

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Program for 3-Bit UP/DOWN Counter ( Behavioral Model ) :-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity updown_3bit_beh is

    Port ( m,clk,pr,clr : in  STD_LOGIC;

           q : out  STD_LOGIC_VECTOR (2 downto 0));

end updown_3bit_beh;

architecture Behavioral of updown_3bit_beh is

begin

process(clk)

variable qh:std_logic_vector(2 downto 0);

begin

if pr='0' then qh:="111";

elsif clr='0' then qh:="000";

elsif clk='1' and clk' event then

          if m='1' then

                   qh:=qh+1;

          else

                   qh:=qh-1;

          end if;

end if ;

q<=qh;

end process;

end Behavioral;library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity updown_3bit_beh is

    Port ( m,clk,pr,clr : in  STD_LOGIC;

           q : out  STD_LOGIC_VECTOR (2 downto 0));

end updown_3bit_beh;

architecture Behavioral of updown_3bit_beh is

begin

process(clk)

variable qh:std_logic_vector(2 downto 0);

begin

if pr='0' then qh:="111";

elsif clr='0' then qh:="000";

elsif clk='1' and clk' event then

          if m='1' then

                   qh:=qh+1;

          else

                   qh:=qh-1;

          end if;

end if ;

q<=qh;

end process;

end Behavioral;