FULL ADDER using Two HALF ADDERS and One Or gate (STRUCTURAL)

FULL ADDER:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end FA;

architecture Structural of FA is
component HA port(a,b:in std_logic;
sum,car:out std_logic);
end component;
component or22 port(a,b:in std_logic;
c:out std_logic);
  end component;
signal x,y,z :std_logic;
begin
u1:HA port map (a,b,x,z);
u2:HA port map (c,x,sum,y);
u3:or22 port map (z,y,carry);

end Structural;

SUB PROGRAM:-

Half Adder:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity HA is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           car : out  STD_LOGIC;

           sum : out  STD_LOGIC);

end HA;

architecture structural of HA is

component and22 port(a,b:in std_logic;

c:out std_logic);

end component;

component xor22 port(a,b:in std_logic;

c:out std_logic);

end component;

begin

u1:xor22 port map(a,b,sum);

u2:and22 port map(a,b,car);

end structural;