Full Subtractor ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_fs_vlog;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire Difference;
wire Borrow;

// Instantiate the Unit Under Test (UUT)
FS_vlog uut (
.a(a),
.b(b),
.c(c),
.Difference(Difference),
.Borrow(Borrow)
);

initial begin
// Initialize Inputs
a = 0; b = 0; c = 0; #100;
a = 0; b = 0; c = 1; #100;
a = 0; b = 1; c = 0; #100;
a = 0; b = 1; c = 1; #100;
a = 1; b = 0; c = 0; #100;
a = 1; b = 0; c = 1; #100;
a = 1; b = 1; c = 0; #100;
a = 1; b = 1; c = 1; #100;
// Add stimulus here

end
     
endmodule

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Program for FULL SUBTRACTOR (  VERILOG  ) :-

module FS_vlog( input a,
      input b,input c,
      output Difference,
      output Borrow );

assign Difference = a ^ b ^ c;
assign Borrow = (~a & b) | (~(a ^ b) & c);
endmodule