4(4-bit) x 1 mux ( Dataflow ) with Test Bench

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_mux_df IS
END tb_mux_df;

ARCHITECTURE behavior OF tb_mux_df IS


    COMPONENT mux_df
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         c : IN  std_logic_vector(3 downto 0);
         d : IN  std_logic_vector(3 downto 0);
         s : IN  std_logic_vector(1 downto 0);
         y : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal c : std_logic_vector(3 downto 0) := (others => '0');
   signal d : std_logic_vector(3 downto 0) := (others => '0');
   signal s : std_logic_vector(1 downto 0) := (others => '0');

   signal y : std_logic_vector(3 downto 0);

BEGIN

   uut: mux_df PORT MAP (
          a => a,
          b => b,
          c => c,
          d => d,
          s => s,
          y => y
        );

   stim_proc: process
   begin
      wait for 100 ns;
a<="0001";b<="0011";c<="1001";d<="1011";
wait for 100 ns;
s<="01";
wait for 100 ns;
s<="10";
wait for 100 ns;
s<="11";

      wait;
   end process;

END;

Program for 4(4-bit) x 1 mux ( Dataflow Model ) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_df is
    Port ( a,b,c,d : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC_VECTOR (3 downto 0));
end mux_df;

architecture Dataflow of mux_df is

begin
y<=a when s="00" else
b when s="01" else
c when s="10" else
d when s="11" ;

end Dataflow;