Multiplexer 4 x 1 ( Verilog ) with Test Fixture

Test Fixture Program :-

module tb_mux_vlog;

// Inputs
reg a;
reg b;
reg c;
reg d;
reg s0;
reg s1;

// Outputs
wire mux_out;

// Instantiate the Unit Under Test (UUT)
Mux_vlog uut (
.a(a),
.b(b),
.c(c),
.d(d),
.s0(s0),
.s1(s1),
.mux_out(mux_out)
);

initial begin
// Initialize Inputs
a = 1; b = 0; c = 1; d = 0; s0 = 0; s1 = 0; #100;
s0 = 1; s1 = 0; #100;
s0 = 0; s1 = 1; #100;
s0 = 1; s1 = 1; #100;
       
// Add stimulus here

end
     
endmodule

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Program for Multiplexer (  VERILOG  ) :-

module Mux_vlog( input a,
      input b,input c,input d,
input s0, input s1,
      output mux_out );

assign mux_out = (a & ~s1 & ~s0) ^ (b & ~s1 & s0) ^ (c & s1 & ~s0) ^ (d & s1 & s0);
endmodule