Encoder ( VERILOG ) with Test Fixture

Test Fixture Program :-

module tf_Encoder_vlog;

// Inputs
reg e;
reg a;
reg b;
reg c;
reg d;

// Outputs
wire firstout;
wire secondout;

// Instantiate the Unit Under Test (UUT)
Encoder_vlog uut (
.e(e),
.a(a),
.b(b),
.c(c),
.d(d),
.firstout(firstout),
.secondout(secondout)
);

initial begin
// Initialize Inputs
e = 0; a = 0; b = 0; c = 0; d = 0; #100;
e = 1; a = 1; b = 0; c = 0; d = 0; #100;
e = 1; a = 1; b = 1; c = 0; d = 0; #100;
e = 1; a = 1; b = 1; c = 1; d = 0; #100;
e = 1; a = 1; b = 1; c = 1; d = 1; #100;
// Add stimulus here

end
     
endmodule


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Program for ENCODER (  VERILOG  ) :-

module Encoder_vlog( input e,
input a, input b, input c, input d,
      output firstout,
output secondout);

assign firstout = (a & b & c) |  (a & b & c & d) ;
assign secondout = (a & b & ~c) | (a & b & c & d) ;
endmodule