JKFF ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_JKFF_vlog;

// Inputs
reg j;
reg k;
reg clr;
reg pr;
reg clk;

// Outputs
wire q;
wire nq;

// Instantiate the Unit Under Test (UUT)
JKFF_vlog uut (
.j(j),
.k(k),
.clr(clr),
.pr(pr),
.clk(clk),
.q(q),
.nq(nq)
);

initial begin
forever begin
clk=0;
#50
clk=1;
#50
clk=0;
end
end

initial begin
j = 0; k = 0; clr = 0; pr = 0; #100;
clr = 0; pr = 1; #100;
clr = 1; pr = 0; #100;
clr = 1; pr = 1; #100;
j = 0; k = 1; #100;
j = 1; k = 0; #100;
j = 1; k = 1; #100;
j = 1; k = 1; #100;
end
     
endmodule


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Program for JKFF (  VERILOG  ) :-

module JKFF_vlog (input j ,input k ,input clr ,
input pr ,input clk , output q , output nq );
reg q;reg nq;
always @ (posedge clk) begin
 if (pr==0) begin
  q = 1;
  nq = 0;
 end else if (clr==0) begin
  nq = 1;
  q = 0;
 end else if (j!=k) begin
  q = j;
  nq = !j;
 end else if (j==0) begin
  q = q;
  nq = nq;
 end else begin
  q = !q;
  nq = !nq;
 end
end

endmodule