3-Bit UP / DOWN Counter ( Structural ) with Test Bench Program

Test Bench Program :-

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_updown_3bit IS

END tb_updown_3bit;

ARCHITECTURE behavior OF tb_updown_3bit IS

    COMPONENT updown_3bit

    PORT(

         m : IN  std_logic;

         clk : IN  std_logic;

         pr : IN  std_logic;

         clr : IN  std_logic;

         q : INOUT  std_logic_vector(2 downto 0)

        );

    END COMPONENT;

   

   signal m : std_logic := '0';

   signal clk : std_logic := '0';

   signal pr : std_logic := '0';

   signal clr : std_logic := '0';

   signal q : std_logic_vector(2 downto 0);

   constant clk_period : time := 10 ns;

BEGIN

   uut: updown_3bit PORT MAP (

          m => m,

          clk => clk,

          pr => pr,

          clr => clr,

          q => q

        );

   clk_process :process

   begin

                   clk <= '0';

                   wait for clk_period/2;

                   clk <= '1';

                   wait for clk_period/2;

   end process;

   stim_proc: process

   begin                

      wait for clk_period;

                   pr<='1';clr<='1';

                   wait for clk_period*8;

                   m<='1';

                   wait for clk_period*5;

                   m<='0';

      wait;

   end process;

END;

Program for 3-Bit UP/DOWN Counter ( Structural Model ) :-

Main Program:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity updown_3bit is

    Port ( m,clk,pr,clr : in  STD_LOGIC;

           q : inout  STD_LOGIC_VECTOR (2 downto 0));

end updown_3bit;

architecture Structural of updown_3bit is

component jkff is

 port(j,k,pr,clr,clk: in std_logic;

   q:out std_logic:='0');

 end component;

component xor_g is

    Port ( a,b : in  STD_LOGIC;

           c : out  STD_LOGIC:='0');

end component;

 signal qh:std_logic_vector(1 downto 0);

begin

jk1:jkff port map ('1','1',pr,clr,clk,q(0));

xorg1:xor_g port map (m,q(0),qh(0));

jk2:jkff port map ('1','1',pr,clr,qh(0),q(1));

xorg2:xor_g port map (m,q(1),qh(1));

jk3:jkff port map ('1','1',pr,clr,qh(1),q(2));

end Structural;

Sub Program (JK FF) :-

library ieee;

use ieee.std_logic_1164.all;

entity jkff is

 port(j,k,pr,clr,clk: in std_logic;

   q:out std_logic:='0');

 end jkff;

architecture behavioral of jkff is

 begin

  process(clk)

 variable temp:std_logic;

 begin

 if clk='1' and clk' event then

 if pr='0' then temp:='1';

 elsif clr='0' then temp:='0';

 elsif j/=k then temp:=j;

 elsif j='1' then temp:=not temp;

 else temp:=temp;

 end if;

 q<=temp;

 end if;

 end process;

 end behavioral;