INTRODUCTION TO VHDL

INTRODUCTION TO VHDL

       VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC programe. In 1983 IBM, Texas instruments and Intermetrics started to develop this language. In 1985 VHDL 7.2 version was released. In 1987 IEEE standardized the language.

Describing a design:

         In VHDL an entity is used to describe a hardware module.

        An entity can be described using,

         1. Entity declaration.

         2. Architecture.

         3. Configuration

         4. Package declaration.

         5. Package body.  

Entity declaration:

    It defines the names, input output signals and modes of a hardware module.

Syntax:
    entity entity_name is
        Port declaration;
    end entity_name; 

       An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.Ports are interfaces through which an entity can communicate with its environment. Each port must have a name, direction and a type. An entity may have no port declaration also. The direction will be input, output or inout

Architecture:

   It describes the internal description of design or it tells what is there inside design. Each entity has atleast one architecture and an entity can have many architecture. Architecture can be described using structural, dataflow, behavioral or mixed style. Architecture can be used to describe a design at different levels of abstraction like gate level, register transfer level (RTL) or behavior level.  

Syntax:

           architecture architecture_name of entity_name
         architecture_declarative_part;
     begin
        Statements;
     end architecture_name; 

      Here we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the begin and end keyword. Architecture declarative part may contain variables, constants, or component declaration.

 Configuration:

     If an entity contains many architectures and  any one of the possible architecture binding with its entity is done using configuration. It is used to bind the architecture body to its entity and a component with an entity. 

Syntax:

    configuration configuration_name of entity_name is

       block_configuration;

    end  configuration_name. 

Block_configuration defines the binding of components in a block. This can be written as  

    for block_name

       component_binding;

    end for;

block_name is the name of the architecture body. Component binding binds the components of the block to entities. This can be written as,         

    for component_labels:component_name

       block_configuration;

    end for;

Package declaration:

  Package declaration is used to declare components, types, constants, functions and so on.

Syntax:   

          package package_name is
       Declarations;
    end package_name; 

Package body:

   A package body is used to declare the definitions and procedures that are declared in corresponding package. Values can be assigned to constants declared in package in package body. 

Syntax:

    package body package_name is
        Function_procedure definitions;
    end package_name;

The internal working of an entity can be defined using different modeling styles inside architcture body. They are

1.      Dataflow modeling.

2.      Behavioral modeling.

3.      Structural modeling. 

Structure of an entity:

Dataflow modeling:

    In this style of modeling, the internal working of an entity can be implemented using concurrent signal assignment.

Let’s take half adder example which is having one XOR gate and a AND gate

Library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity ha_en is  

            port (A,B:in std_logic;S,C:out std_logic);

end ha_en;

architecture ha_ar of ha_en is

begin               

            S<=A xor B;

            C<=A and B;

end ha_ar; 

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The architecture body consists of concurrent signal assignments, which describes the functionality of the design. Whenever there is a change in RHS, the expression is evaluated and the value is assigned to LHS. 

Behavioral modeling:

    In this style of modeling, the internal working of an entity can be implemented using set of statements.

      It contains:

·            Process statements

·            Sequential statements

·            Signal assignment statements

·            Wait statements

Process statement is the primary mechanism used to model the behavior of an entity. It contains sequential statements, variable assignment (:=) statements or signal assignment (<=) statements etc. It may or may not contain sensitivity list. If there is an event occurs on any of the signals in the sensitivity list, the statements within the process is executed.

Inside the process the execution of statements will be sequential and if one entity is having two processes the execution of these processes will be concurrent. At the end it waits for another event to occur. 

Structural modeling:

   The implementation of an entity is done through set of interconnected components.

It contains:

·          Signal declaration.

·          Component instances

·          Port maps.

·          Wait statements.

 Component declaration:

   Syntax:

      component component_name [is]

        List_of_interface ports;

     end component component_name;  

Before instantiating the component it should be declared using component declaration as shown above. Component declaration declares the name of the entity and interface of a component.

Basic VHDL Statement – Syntax:

Library Syntax:

Library <Library_Name>;

Use <Library_Name>.<Package_Name>.<Package_Parts>;

Component Instantiation Syntax:

Label: <Component_Name> Portmap (Signal mapping);

Signal Declaration Syntax:

Signal <Signal_Name>: Signal_Type (Range):= ‘Initial Value’

 Variable Declaration Syntax:

 Variable <Variable_Name>: Variable_ Type (Range):= ‘Initial Value’;

Constant Declaration Syntax:

Constant <Constant_Name>: Constant_ Type (Range):= ‘Initial Value’;

Simple When/Else Syntax:

 Assignment When Condition Else

 Assignment When Condition Else;

With/Select/When:

With <identifier> Select 

Assignment When Value, 

Assignment When Value;

(Whenever With/Select/When is used, all permutations must be tested.)

Process Syntax:

Label: Process (Sensitivity List)

<Variable Declaration>;

Begin

<Sequential Statements>;

End Process label;

If Statement Syntax:

 If <Condition> Then <Assignments>;

Elsif <Condition> Then <Assignments>;

…….Else <Assignments>;

End If;

Case Statement Syntax:

Case <identifier> is

When value => assignments;

When value => assignments;

End Case;

While Loop Statement;

Label: While <Condition> Loop

<Sequential Statements>;

End Loop;

For Loop Statement:

Label: For <identifier> In < range>Loop

<Sequential Statements>;

End Loop;

Wait Statement Syntax:

Wait Until <Signal_Condition>;

Wait On Signal<Signal1, Signal2...>;

Wait For <time>;

Wait statement when used inside process statement does not need sensitivity list in process statement.