64 x 1 MULTIPLEXER using 8 x 1 multiplexer (Structural)

64 x 1  MULTIPLEXER:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_64_1 is
    Port ( I : in  STD_LOGIC_VECTOR (0 to 63);
           s : in  STD_LOGIC_VECTOR (5 downto 0);
           Y : out  STD_LOGIC);
end mux_64_1;

architecture Behavioral of mux_64_1 is

component muxs is
    Port ( I : in  STD_LOGIC_VECTOR (0 to 7);
           s : in  STD_LOGIC_VECTOR (2 downto 0);
       
           Y : out  STD_LOGIC);
end component;

signal x:std_logic_vector(0 to 7);

begin
u1:muxs port map(I(0 to 7),S(2 downto 0),x(0));
u2:muxs port map(I(8 to 15),S(2 downto 0),x(1));
u3:muxs port map(I(16 to 23),S(2 downto 0),x(2));
u4:muxs port map(I(24 to 31),S(2 downto 0),x(3));
u5:muxs port map(I(32 to 39),S(2 downto 0),x(4));
u6:muxs port map(I(40 to 47),S(2 downto 0),x(5));
u7:muxs port map(I(48 to 55),S(2 downto 0),x(6));
u8:muxs port map(I(56 to 63),S(2 downto 0),x(7));
u9:muxs port map(x,s(5 downto 3),Y);

end Behavioral;

Mux, Subprogram:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity muxs is
    Port ( I : in  STD_LOGIC_VECTOR (0 to 7);
           s : in  STD_LOGIC_VECTOR (2 downto 0);
       
           Y : out  STD_LOGIC);
end muxs;

architecture Dataflow of muxs is

begin
with s select
Y<= I(0) when "000",
I(1) when "001",
I(2) when "010",
I(3) when "011",
I(4) when "100",
I(5) when "101",
I(6) when "110",
I(7) when others;

end Dataflow;

OUT PUT:-

Test bench:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tbmx IS
END tbmx;

ARCHITECTURE behavior OF tbmx IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT mux_64_1
    PORT(
         I : IN  std_logic_vector(0 to 63);
         s : IN  std_logic_vector(5 downto 0);
         Y : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal I : std_logic_vector(0 to 63) := (others => '0');
   signal s : std_logic_vector(5 downto 0) := (others => '0');

  --Outputs
   signal Y : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

 

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: mux_64_1 PORT MAP (
          I => I,
          s => s,
          Y => Y
        );


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.

I<= conv_std_logic_vector(2751055,64);
     for i in 0 to 63 loop

      s<=  conv_std_logic_vector(i,6);
 wait for 100 ns;
 end loop;
   

      -- insert stimulus here

      wait;
   end process;

END;