64 x 1 MULTIPLEXER using 8 x 1 multiplexer (Structural) with the help of "GENERATE"

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux_64_1 is

    Port ( I : in  STD_LOGIC_VECTOR (0 to 63);

           s : in  STD_LOGIC_VECTOR (5 downto 0);

           Y : out  STD_LOGIC);

end mux_64_1;

architecture Behavioral of mux_64_1 is

component muxs is

    Port ( I : in  STD_LOGIC_VECTOR (0 to 7);

           s : in  STD_LOGIC_VECTOR (2 downto 0);

          

           Y : out  STD_LOGIC);

end component;

signal x:std_logic_vector(0 to 7);

begin

u9:muxs port map(x,s(5 downto 3),Y);

  lb: for j in 0 to 7 generate

          ux:muxs port map(I(8*j to 8*j+7),S(2 downto 0),x(j));

 end generate;

end Behavioral;