VHDL vs VERILOG
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വാഴയൂർ ഗ്രാമ പഞ്ചായത്ത് ( Vazhayur Grama Panchayath )
Sunday, 13 November 2016
NOR Gate in Verilog
module nor_code(
input input_a,
input input_b,
output output_c
);
assign output_c = input_a ~| input_b ;
endmodule
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