OR ( VERILOG ) with Text Fixture

Test Fixture Program :-

module tf_ORing_code;

// Inputs
reg input_a;
reg input_b;

// Outputs
wire output_c;

// Instantiate the Unit Under Test (UUT)
ORing_code uut (
.input_a(input_a),
.input_b(input_b),
.output_c(output_c)
);

initial begin
// Initialize Inputs
input_a = 0;
input_b = 0;

// Wait 100 ns for global reset to finish
#100;
input_a = 0; input_b = 1; #100;
input_a = 1; input_b = 0; #100;
input_a = 1; input_b = 1; #100;
     
// Add stimulus here

end
   
endmodule


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Program for OR (  VERILOG  ) :-

module ORing_code(
    input input_a,
    input input_b,
    output output_c
    );

assign output_c = input_a | input_b ;

endmodule