Monday, 14 November 2016

Ripple Carry Adder Dataflow with Testbench Program





Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_rca_dflow IS
END tb_rca_dflow;

ARCHITECTURE behavior OF tb_rca_dflow IS

    COMPONENT rca_dflow
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         Cin : IN  std_logic;
         Cout : INOUT  std_logic;
         s : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal Cin : std_logic := '0';

   signal Cout : std_logic;

   signal s : std_logic_vector(3 downto 0);
BEGIN
    uut: rca_dflow PORT MAP (
          a => a,
          b => b,
          Cin => Cin,
          Cout => Cout,
          s => s
        );
   stim_proc: process
   begin                
      wait for 100 ns;
                   a<="0010";b<="1011";
      wait for 100 ns;
                   a<="1010";b<="1011";
      wait for 100 ns;
                   a<="1110";b<="1011";cin<='1';
      wait for 100 ns;
                   a<="1110";b<="1111";cin<='1';
      wait for 100 ns;
                   a<="1110";b<="0101";cin<='1';
      wait;
   end process;


END;

--------------------------------------------------------------------------------------------------------------------------

Program for Ripple Carry Adder ( Dataflow Model ) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity rca_dflow is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           Cin : in  STD_LOGIC;
           Cout : inout  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0));
end rca_dflow;

architecture Dataflow of rca_dflow is

signal p: std_logic_vector(3 downto 0);
signal g: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 1);

begin
p<=a xor b;
g<=a and b;
c(1)<=g(0) or (p(0) and cin);
c(2)<=g(1) or (p(1) and c(1));
c(3)<=g(2) or (p(2) and c(2));
cout<=g(3) or (p(3) and c(3));
s(0)<=p(0) xor cin;
s(1)<=p(1) xor c(1);
s(2)<=p(2) xor c(2);
s(3)<=p(3) xor c(3);

end Dataflow;






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