Demux 1 x 4 ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_demux_vlog;

// Inputs
reg a;
reg s0;
reg s1;

// Outputs
wire mux_firstout;
wire mux_secondout;
wire mux_thirdout;
wire mux_fourthout;

// Instantiate the Unit Under Test (UUT)
Demux_vlog uut (
.a(a),
.s0(s0),
.s1(s1),
.mux_firstout(mux_firstout),
.mux_secondout(mux_secondout),
.mux_thirdout(mux_thirdout),
.mux_fourthout(mux_fourthout)
);

initial begin
// Initialize Inputs
a = 0; s0 = 0; s1 = 0; #100;
a = 1; s0 = 0; s1 = 0; #100;
a = 1; s0 = 0; s1 = 1; #100;
a = 1; s0 = 1; s1 = 0; #100;
a = 1; s0 = 1; s1 = 1; #100;
       
// Add stimulus here

end
     
endmodule


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Program for Demux (  VERILOG  ) :-

module Demux_vlog( input a,
input s0, input s1,
      output mux_firstout,
output mux_secondout,
output mux_thirdout,
output mux_fourthout);

assign mux_firstout = (a & ~s1 & ~s0) ;
assign mux_secondout = (a & ~s1 & s0) ;
assign mux_thirdout = (a & s1 & ~s0) ;
assign mux_fourthout = (a & s1 & s0) ;
endmodule