Test bench Program for Sequence Detector For the Sequence "1011" (Mealy Model)

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_seqdet1 IS
END tb_seqdet1;

ARCHITECTURE behavior OF tb_seqdet1 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT seqdet1
    PORT(
         a : IN  std_logic;
         clk : IN  std_logic;
         clr : IN  std_logic;
         a_pe : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal clk : std_logic := '0';
   signal clr : std_logic := '0';

  --Outputs
   signal a_pe : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: seqdet1 PORT MAP (
          a => a,
          clk => clk,
          clr => clr,
          a_pe => a_pe
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.

      wait for clk_period;
a<='1';clr<='1';
wait for clk_period;
a<='0';
wait for clk_period;
a<='1';
wait for clk_period;
a<='1';

      -- insert stimulus here

      wait;
   end process;

END;

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Program for Sequence Detector for the sequence 1011 :-

library ieee;
use ieee.std_logic_1164.all;

entity seqdet1 is
port (a,clk,clr:in std_logic;
a_pe:out std_logic);
end seqdet1;

architecture fsm of seqdet1 is
type state is(state_a,state_b,state_c,state_d);
signal present_state,next_state:state;
begin

Clock_process:process(clk,clr)
begin
if clk' event and clk='1' then
if clr='0' then
present_state <= state_a;
else
present_state<=next_state;
end if;
end if;
end process;

Output_process:process(clk)
begin
if clk' event and clk='1' then
if present_state=state_d and a='1' then
a_pe<='1';
else
a_pe<='0';
end if;
end if;
end process;

State_process:process(present_state,a)
begin
case present_state is
when state_a=>
if a='0' then
next_state<= state_a;
else
next_state<=state_b;
end if;

when state_b=>
if a='0' then
next_state<= state_c;
else
next_state<=state_b;
end if;

when state_c=>
if a='0' then
next_state<=state_a;
else
next_state<=state_d;
end if;

when others=>
if a='0' then
next_state<=state_c;
else
next_state<=state_a;
end if;
end case;
end process;

end fsm;