Test bench for 4 bit Up-Counter

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_counter_4bit IS
END tb_counter_4bit;

ARCHITECTURE behavior OF tb_counter_4bit IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT counter_4bit
    PORT(
         clr : IN  std_logic;
         pr : IN  std_logic;
         clk : IN  std_logic;
         q : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal clr : std_logic := '0';
   signal pr : std_logic := '0';
   signal clk : std_logic := '0';

  --Outputs
   signal q : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 60 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: counter_4bit PORT MAP (
          clr => clr,
          pr => pr,
          clk => clk,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.

      wait for clk_period*10;

      -- insert stimulus here

      wait;
   end process;

END;

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Program for 4bit Up-Counter :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity counter_4bit is
    Port ( clr,pr : in  STD_LOGIC:='1';
           clk : in  STD_LOGIC;
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end counter_4bit;

architecture Behavioral of counter_4bit is

begin
process(clk)
variable temp : std_logic_vector(3 downto 0):="0000";
begin
if rising_edge(clk) then
temp := temp + '1';
end if;
q <= temp;
end process;

end Behavioral;