Johnson Reverse-Johnson Counter ( 8bit ) Behavioral (Clock divided by 2^27)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity rj_counter_v is
    Port ( clk : in  STD_LOGIC;
           q : out  STD_LOGIC_VECTOR (7 downto 0));
end rj_counter_v;

architecture Behavioral of rj_counter_v is

signal qt: STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
signal clk_g,m:  STD_LOGIC:='0';
signal t_5 : STD_LOGIC_VECTOR (4 downto 0):=(0=>'1',others=>'0');
signal t_27 : STD_LOGIC_VECTOR (26 downto 0):=(others=>'0');

begin

  prc_div: process(clk) begin
if(clk' event and clk='1') then
if(t_27=X"FFFFFF7") then
t_27<=(others=>'0');
else
t_27<=t_27+1;
end if;
end if;
  end process;

 
clk_g<=t_27(26);

 process(clk_g) begin
   if(clk_g'event and clk_g='1') then
if t_5=X"F1" then
t_5<=(others=>'0');
else
t_5<=t_5+1;
end if;

m<=t_5(4);

if m='0' then
qt(7)<= not qt(0);
qt(6 downto 0)<= qt(7 downto 1);
else
qt(0)<= not qt(7);
qt(7 downto 1)<= qt(6 downto 0);
end if;
end if;
end process;

  q<=qt;
   
end Behavioral;