Half Adder ( VERILOG ) with Text Fixture

Test Fixture Program :-

module tf_ha;

// Inputs
reg a;
reg b;

// Outputs
wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)
HA_vlog uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish
#100;
a = 0; b = 1; #100;
a = 1; b = 0; #100;
a = 1; b = 1; #100;
       
// Add stimulus here

end
     
endmodule

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Program for HALF ADDER (  VERILOG  ) :-

module HA_vlog( input a,
input b,
output sum,
output carry );

assign sum = a ^ b;
assign carry = a & b;
endmodule