Test Bench Program :-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_ha_df IS
END tb_ha_df;
ARCHITECTURE behavior OF tb_ha_df IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ha_df
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ha_df PORT MAP (
a => a,
b => b,
sum => sum,
carry => carry
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a<='0';b<='0';
wait for 100 ns;
a<='0';b<='1';
wait for 100 ns;
a<='1';b<='0';
wait for 100 ns;
a<='1';b<='1';
-- insert stimulus here
wait;
end process;
END;
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Program for HALF ADDER ( Dataflow ) :-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha_df is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha_df;
architecture Dataflow of ha_df is
begin
sum <= a xor b ;
carry <= a and b ;
end Dataflow;
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