Write Data to a File in VHDL ( Here to .doc)

library IEEE;
use std.textio.all;

entity filehandle is
end filehandle;

architecture Behavioral of filehandle is

signal clock,endoffile : bit := '0';
signal    linenumber : integer:=1;
begin
clock <= not (clock) after 1 ns;

writing :process
file      outfile  : text is out "aabc.doc";  --declare output file
variable  outline  : line;
begin
wait until clock = '0' and clock' event;
if linenumber<2 then
write(outline, " "&"www.vhdl4all.blogspot.in");
writeline(outfile, outline);
linenumber <= linenumber + 1;
else
null;
end if;
end process writing;

end Behavioral;