Test bench Program for AND - Gate

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_and_2 IS
END tb_and_2;

ARCHITECTURE behavior OF tb_and_2 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT and_2
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         y : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

  --Outputs
   signal y : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: and_2 PORT MAP (
          a => a,
          b => b,
          y => y
        );

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
a<='0';b<='0';
      wait for 100 ns;
a<='0';b<='1';
      wait for 100 ns;
a<='1';b<='0';
      wait for 100 ns;
a<='1';b<='1';

      -- insert stimulus here

      wait;
   end process;

END;

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Program for AND - Gate ( Dataflow Model ) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           y : out  STD_LOGIC);
end and_2;

architecture Dataflow of and_2 is

begin
y <= a and b ;

end Dataflow;