Test bench Program for HALF SUBTRACTOR

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_hs_df IS
END tb_hs_df;

ARCHITECTURE behavior OF tb_hs_df IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT hs_df
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         difference : OUT  std_logic;
         borrow : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

  --Outputs
   signal difference : std_logic;
   signal borrow : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: hs_df PORT MAP (
          a => a,
          b => b,
          difference => difference,
          borrow => borrow
        );

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
a<='0';b<='0';
      wait for 100 ns;
a<='0';b<='1';
      wait for 100 ns;
a<='1';b<='0';
      wait for 100 ns;
a<='1';b<='1';
      -- insert stimulus here

      wait;
   end process;

END;

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Program for HALF SUBTRACTOR ( Dataflow ) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hs_df is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           difference : out  STD_LOGIC;
           borrow : out  STD_LOGIC);
end hs_df;

architecture Dataflow of hs_df is

begin
difference <= a xor b ;
borrow <= ( not a ) and b ;
end Dataflow;