4 x 1 Mux Dataflow with Testbench

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_mux_4x1 IS
END tb_mux_4x1;

ARCHITECTURE behavior OF tb_mux_4x1 IS

    COMPONENT Mux_4x1
    PORT(
         x : IN  std_logic_vector(0 to 3);
         s : IN  std_logic_vector(1 downto 0);
         y : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal x : std_logic_vector(0 to 3) := (others => '0');
   signal s : std_logic_vector(1 downto 0) := (others => '0');

  --Outputs
   signal y : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: Mux_4x1 PORT MAP (
          x => x,
          s => s,
          y => y
        );

   -- Stimulus process
   stim_proc: process
   begin
      wait for 100 ns;
x<="0101";s<="00";
      wait for 100 ns;
s<="01";
      wait for 100 ns;
s<="10";
      wait for 100 ns;
s<="11";
      wait;
   end process;

END;

--------------------------------------------------------------------------------------------------------------------------

Program for Mux :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Mux_4x1 is
    Port ( x : in  STD_LOGIC_VECTOR (0 to 3);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end Mux_4x1;

architecture Dataflow of Mux_4x1 is

begin
y<=(x(0) and not s(1) and not s(0)) or (x(1) and not s(1) and s(0)) or
(x(2) and s(1) and not s(0)) or (x(3) and s(1) and s(0));
end Dataflow;