Write Data to a File in VHDL ( Here to .txt)

Write Data to a File in VHDL ( Here to .doc)

Johnson Reverse-Johnson Counter ( 8bit ) Behavioral (Clock divided by 2^27)

8 bit Johnson Counter Behavioral (Clock divided by 2^27)

4 x 1 Mux Dataflow with Testbench

FPGA Design Steps

Half Adder ( VERILOG ) with Text Fixture

Test bench Program for HALF SUBTRACTOR

Test bench Program for HALF ADDER

Test bench Program for AND - Gate

Test bench Program for Sequence Detector For the Sequence "1011" (Mealy Model)