Serail In Serial Out Shift Register With the Help of Loop Statement

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 entity siso_looped is
port(clk,s_in: in std_logic;
s_out: out std_logic);
end siso_looped;

architecture behavioral of siso_looped is
signal q : std_logic_vector (3 downto 0):="0000";
begin
process(clk)
begin
if rising_edge(clk) then
q(3)<=s_in;
for i in 2 downto 0 loop
q(i) <= q(i+1);
end loop;
end if;
s_out<=q(0);
end process;
end behavioral;