library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tff is
Port ( t,clk,clr,pr : in STD_LOGIC;
q : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
begin
process(clk)
variable x : std_logic:='0';
begin
if rising_edge(clk) then
if pr='0' then x:='1';
elsif clr='0' then x:='0';
elsif t='0' then x:=x;
else x:=not x;
end if;
end if;
q<=x;
end process;
end Behavioral;
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