Test bench for Toggle Flip-Flop

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_tff IS
END tb_tff;

ARCHITECTURE behavior OF tb_tff IS

    COMPONENT tff
    PORT(
         t : IN  std_logic;
         clk : IN  std_logic;
         clr : IN  std_logic;
         pr : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
 
   --Inputs
   signal t : std_logic := '0';
   signal clk : std_logic := '0';
   signal clr : std_logic := '0';
   signal pr : std_logic := '0';

  --Outputs
   signal q : std_logic;

   -- Clock period definitions
   constant clk_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: tff PORT MAP (
          t => t,
          clk => clk,
          clr => clr,
          pr => pr,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin

t<='0';clr<='1';pr<='0';
      wait for clk_period;
t<='0';clr<='0';pr<='1';
      wait for clk_period;
t<='0';clr<='1';pr<='1';
      wait for clk_period;
t<='1';
      wait for clk_period*3;

   end process;

END;

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Program for Toggle Flip-Flop :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity tff is
    Port ( t,clk,clr,pr : in  STD_LOGIC;
           q : out  STD_LOGIC);
end tff;

architecture Behavioral of tff is

begin
process(clk)
variable x : std_logic:='0';
begin
if rising_edge(clk) then
if pr='0' then x:='1';
elsif clr='0' then x:='0';
elsif t='0' then x:=x;
else x:=not x;
end if;
end if;
q<=x;
end process;

end Behavioral;