Delay Flip-Flop with the help of 'Variable'

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity dff is
    Port ( d,clk,clr,pr : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(clk)
variable x : std_logic:='0';
begin
if rising_edge(clk) then
if pr='0' then x:='1';
elsif clr='0' then x:='0';
else x:=d;
end if;
end if;
q<=x;
end process;

end Behavioral;