library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pr_encdr_4_2 is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(1 downto 0)
);
end pr_encdr_4_2;
architecture pr_encdr_df of pr_encdr_4_2 is
begin
dout <= "00" when std_match (din,"1---") else
"01" when std_match (din,"01--") else
"10" when std_match (din,"001-") else
"11" when std_match (din,"0001");
end pr_encdr_df;
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