SR Flip-Flop with the help of 'Variable'

library ieee;
use ieee.std_logic_1164.all;

entity srff is
 port(s,r,pr,clr,clk: in std_logic;
   q:out std_logic:='0');
 end srff;

architecture behavioral of srff is
 begin

 process(clk)
 variable temp:std_logic;
 begin
 if clk='1' and clk' event then
 if pr='0' then temp:='1';
 elsif clr='0' then temp:='0';
 elsif s/=r then temp:=s;
 elsif s='1' then temp:='U';
 else temp:=temp;
 end if;
 q<=temp;
 end if;
 end process;

 end behavioral;