library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
Port ( clk, clr,
pr, T :in STD_LOGIC ;
Q ,Q_n :
inout STD_LOGIC );
end T_FF;
architecture Behavioral of T_FF is
begin
process (clk, clr, pr, T)
begin
if pr = '0' then Q<='1';Q_n<='0';
elsif clr ='0' then Q<='0';Q_n<='1';
elsif clk='1' and clk'event then
if T='0' then
Q<=Q; Q_n<=Q_n;
else Q<=Q_n
;Q_n<= Q;
end if;
end if;
end process;
end Behavioral;
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