use IEEE.STD_LOGIC_1164.ALL;
entity Eccess_three is
Port ( B2,B1,B0 : in STD_LOGIC;
E3,E2,E1,E0 : out STD_LOGIC);
end Eccess_three;
architecture Dataflow of Eccess_three is
begin
E3<=B2 and (B1 or B0);
E2<=B2 xor (B1 or B0);
E1<=B1 xnor B0;
E0<=not B0;
end Dataflow;
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