library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is
Port ( clk, clr, pr,D :in STD_LOGIC ;
Q ,Q_n : out
STD_LOGIC );
end D_FF;
architecture Behavioral of D_FF is
begin
process (clk, clr, pr,D)
begin
if pr = '0' then Q<='1';Q_n<='0';
elsif clr ='0' then Q<='0';Q_n<='1';
elsif clk='1' and clk'event then
if D='0' then Q<='0';Q_n<='1';
else Q<='1'; Q_n<='0';
end if;
end if;
end process;
end Behavioral;
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