library ieee;
use ieee.std_logic_1164.all;
Entity J_COUNTER is
port(clr,clk,pr:in
std_logic;Q:inout std_logic_vector(0 to 3));
end J_COUNTER;
Architecture behavioral of
J_COUNTER is
begin
process( clr,clk,pr)
begin
if (pr ='0') then Q<="1111";
elsif (clr ='0') then
Q<="0000";
elsif clk='1' and clk'event then
Q(0)<=not
Q(3);Q(1)<=Q(0);Q(2)<=Q(1);Q(3)<=Q(2);
end if;
end process;
end behavioral;
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