Function Implementation ( Verilog ) with Test Fixture

This is a program to Implement the function for getting output at 1,3,4,6,7,8,9,13 ... ...

Test Fixture Program :-

module tf_functn1_vlog;


reg a;
reg b;
reg c;
reg d;


wire functionout;


functn1_vlog uut (
.a(a),
.b(b),
.c(c),
.d(d),
.functionout(functionout)
);

initial begin

a = 0;b = 0;c = 0;d = 0;#100;
a = 0;b = 0;c = 0;d = 1;#100;
a = 0;b = 0;c = 1;d = 0;#100;
a = 0;b = 0;c = 1;d = 1;#100;
a = 0;b = 1;c = 0;d = 0;#100;
a = 0;b = 1;c = 0;d = 1;#100;
a = 0;b = 1;c = 1;d = 0;#100;
a = 0;b = 1;c = 1;d = 1;#100;
a = 1;b = 0;c = 0;d = 0;#100;
a = 1;b = 0;c = 0;d = 1;#100;
a = 1;b = 0;c = 1;d = 0;#100;
a = 1;b = 0;c = 1;d = 1;#100;
a = 1;b = 1;c = 0;d = 0;#100;
a = 1;b = 1;c = 0;d = 1;#100;
a = 1;b = 1;c = 1;d = 0;#100;
a = 1;b = 1;c = 1;d = 1;#100;
     

end
   
endmodule


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Program for Function Implementation (  VERILOG  ) :-

module functn1_vlog(input a,
  input b, input c, input d,
  output functionout);

assign functionout = (~a & ~b & d) | (~a & b & ~d) |(~a & c & d) |(a & ~c & d) |(a & ~b & ~c) ;
endmodule