Verilog Syntax

Verilog Syntax 

1. Module & Instantiation of Instances

A Module in Verilog is declared within the pair of keywords module and endmodule. Following the keyword module are the module name and port interface list.
module my_module ( a, b, c, d );
 input a, b;
 output c, d;
 ...
 endmodule

   All instances must be named except the instances of primitives. Only primitives in Verilog can have anonymous instances, i.e. and, or, nand, nor, xor, xnor, buf, not, bufif1, bufi0, notif1, notif0, nmos, pmos, cmos, tran, tranif1, tranif0, rnmos, rpmos, rcmos, rtran, rtranif1, rtranif0.

 Port Connections at Instantiations
 In Verilog, there are 2 ways of specifying connections among ports of instances.

a) By ordered list (positional association) This is the more intuitive method, where the signals to be connected must appear in the module instantiation in the same order as the ports listed in module definition.

b) By name (named association) When there are too many ports in the large module, it becomes difficult to track the order. Connecting the signals to the ports by the port names increases readability and reduces possible errors.
module top;
 reg A, B;
 wire C, D;
 my_module m1 (A, B, C, D); // By order
 my_module m2 (.b(B), .d(D), .c(C), .a(A)); // By name
 ...

endmodule

 Parameterized Instantiations

The values of parameters can be overridden during instantiation, so that each instance can be customized separately. Alternatively, defparam statement can be used for the same purpose


Conditional Statements 

  The body only allows a single statement.  If multiple statements are desired, block
statements may be used to enclose multiple statements in place of the body.

  a)  If-Then-Else
  if ( expr )
    statement;
 
if ( expr )
  statement;
  else
    statement;
 
if ( expr ) statement;
  else if ( expr ) statement;
  else if ( expr ) statement;
  else statement;

  b) Case
  case ( expr )
    value1 : statement;
    value2 : statement;
    value3 : statement;
      ...
    default : statement;
  endcase


Loop Statements

  The body only allows a single statement.  If multiple statements are desired, block
statements may be used to enclose multiple statements in place of the body.

  a)  While
  while ( expr )
    statement;

  b) For
  for ( init ; expr ; step )
    statement;

  c)  Repeat
    Iterations are based on a constant instead of conditional expression.
  repeat ( constant )    // Fix number of loops
    statement;

  d) Forever
  forever        // Same as while (1)
    statement;