Priority Selector ( Verilog ) with Test Fixture

This is a program to select three output on the basis of priority ... ...

Test Fixture Program :-

module tf_Ps_vlog;

reg a;
reg b;
reg c;

wire firstout;
wire secondout;
wire thirdout;

Ps_vlog uut (
.a(a),
.b(b),
.c(c),
.firstout(firstout),
.secondout(secondout),
.thirdout(thirdout)
);

initial begin

a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;
end
   
endmodule



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Program for Function Implementation (  VERILOG  ) :-

module Ps_vlog(
  input a, input b, input c,
      output firstout,
  output secondout,output thirdout);

assign firstout = a;
assign secondout = ~a & b;
assign thirdout = ~a & ~b & c;
endmodule