UP / DOWN Counter ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_up_down_counter;

// Inputs
reg up_down;
reg clk;
reg reset;

// Outputs
wire [7:0] out;

// Instantiate the Unit Under Test (UUT)
up_down_counter uut (
.out(out),
.up_down(up_down),
.clk(clk),
.reset(reset)
);
initial begin
clk=1'b1;
forever #5 clk=~clk;
end


initial begin
up_down = 0;reset = 1;#10;
reset = 0;#30;
up_down = 1;#10;
up_down = 0;
end


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Program for Up / Down Counter (  VERILOG  ) :-

module up_down_counter    (
out      ,  // Output of the counter
 up_down  ,  // up_down control for counter
 clk      ,  // clock input
 reset       // reset input
 );
 //----------Output Ports--------------
  output [7:0] out;
  //------------Input Ports--------------
  input up_down, clk, reset;
  //------------Internal Variables--------
  reg [7:0] out;
  //-------------Code Starts Here-------
  always @(posedge clk)
  if (reset) begin // active high reset
    out <= 7'b0 ;
  end else if (up_down) begin
    out <= out + 1;
  end else begin
    out <= out - 1;
 end

  endmodule