UP Counter ( Verilog ) with Test Fixture

Test Fixture Program :-
module tf_up_counter;

// Inputs
reg clk;
reg reset;

// Outputs
wire [7:0] out;

// Instantiate the Unit Under Test (UUT)
up_counter uut (
.out(out),
.clk(clk),
.reset(reset)
);

initial begin
clk=1'b1;
forever #5 clk=~clk;
end


initial begin
reset = 1;#10;
reset = 0;#30;

end
   
endmodule


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Program for Up Counter (  VERILOG  ) :-

module up_counter    (
 out      ,  // Output of the counter
 clk      ,  // clock input
 reset       // reset input
 );
 //----------Output Ports--------------
  output [7:0] out;
  //------------Input Ports--------------
  input clk, reset;
  //------------Internal Variables--------
  reg [7:0] out;
  //-------------Code Starts Here-------
  always @(posedge clk)
  if (reset) begin // active high reset
    out <= 7'b0 ;
  end else begin
    out <= out + 1;
 end

  endmodule