library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity sg is
Port ( clk,clr,pr : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end sg;
architecture Behavioral of sg is
begin
process(clk,clr,pr)
begin
if pr='0' then q<="1111";
elsif clr='0' then q<="0000";
elsif clk='0' and clk'event then
if q="0000" then q<="0100";
elsif q="1111" then q<="0001";
elsif q="1111" then q<="0001";
elsif q="0100" then q<="0101";
elsif q="0101" then q<="0011";
elsif q="0011" then q<="0010";
elsif q="0010" then q<="0100";
end if;
end if;
end process;
end Behavioral;
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