RING COUNTER (Structural)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity R_C is

    Port ( clk,clr,pr : in  STD_LOGIC;

           q : inout  STD_LOGIC_VECTOR (3 downto 0));

end R_C;

architecture Struct of R_C is

component md is

port (clk,clr,pr,d:in  STD_LOGIC;q: inout  STD_LOGIC);

end component;

component mor4 is

port(a,b,c,d:in  STD_LOGIC;e:out  STD_LOGIC);

end component;

component mnot

port(a:in  STD_LOGIC;b:out  STD_LOGIC);

end component;

component mor is

port(a,b:in  STD_LOGIC;c:out  STD_LOGIC);

end component;

signal e,f,g:STD_LOGIC;

begin

u1:mor4 port map (q(2),q(1),q(3),q(0),e);

u2:mnot port map (e,f);

u3:mor port map (f,q(0),g);

u4:md port map (clk,clr,pr,g,q(3));

u5:md port map (clk,clr,pr,q(3),q(2));

u6:md port map (clk,clr,pr,q(2),q(1));

u7:md port map (clk,clr,pr,q(1),q(0));

end Struct;