4-BIT UP COUNTER (Structural)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity upc is

    Port ( clk,clr,pr : in  STD_LOGIC;

           q : inout  STD_LOGIC_VECTOR (3 downto 0));

end upc;

architecture structoral of upc is

component mjk

port (clk,clr,pr,j,k :in std_logic;

                                q:inout std_logic);

end component;

begin

u1:mjk port map (clk,clr,pr,'1','1',q(0));

u2:mjk port map (q(0),clr,pr,'1','1',q(1));

u3:mjk port map (q(1),clr,pr,'1','1',q(2));

u4:mjk port map (q(2),clr,pr,'1','1',q(3));

end structoral;