library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
Entity UP_COUNTER is
port(clr,clk,pr:in std_logic;Q:inout std_logic_vector(3 downto 0));
end UP_COUNTER;
Architecture behavioral of UP_COUNTER is
begin
process( clr,clk,pr,Q)
begin
if (pr ='0') then Q<="1111";
elsif (clr ='0') then Q<="0000";
elsif clk='0' and clk'event then
Q<=Q + 1;
elsif (Q="1010") then Q<="0000";
end if;
end process;
end behavioral;
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