JOHNSON COUNTER (Structural)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity jc is

    Port ( clk,clr,pr,d : in  STD_LOGIC;

           q : inout  STD_LOGIC_VECTOR (3 downto 0));

end jc;

architecture Structural of jc is

component df

port (clk, clr,pr, d:in std_logic;

                                q:inout std_logic);

                end component;

                signal qn: std_LOGIC; 
component mnot
port(a:in std logic; b:out std_logic);
end component;  

begin

u1:mnot port map (q(0),qn);

u2: df port map (clk,clr,pr,qn,q(3));

u3: df port map (clk,clr,pr,q(3), q(2));

u4: df port map (clk,clr,pr,q(2),q(1));

u5: df port map (clk,clr,pr,q(1),q(0));

end Structural;