Ring / Johnson Counter ( Verilog ) with Testfixture

Test Fixture Program :-

module tf_ring_johnson_vlog_new;

// Inputs
reg clk;
reg reset;
reg mode;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)
ring_vlog_new uut (
.out(out),
.clk(clk),
.reset(reset),
.mode(mode)
);

initial begin
clk=1'b1;
forever #5 clk=~clk;
end


initial begin

reset = 1;mode=1;#10;
reset = 1;#10;
reset = 0;#40;
reset = 1;mode=0;#10;
reset = 1;#10;
reset = 0;#30;

end
 
endmodule


--------------------------------------------------------------------------------------------------------------------------

Program for Ring / Johnson Counter (  VERILOG  )  :-

module ring_johnson_vlog_new(
 out      ,  // Output of the counter
 clk      ,  // clock input
 reset,mode       // reset input
 );
 //----------Output Ports--------------
  output [3:0] out;
  //------------Input Ports--------------
  input clk, reset,mode;
  //------------Internal Variables--------
  reg [3:0] out;
  //-------------Code Starts Here-------
  always @(posedge clk)
if (reset)
begin // active high reset
out <= 4'b0001 ;
end
else if (mode==1'b1)
begin
out <= {out[2:0],out[3]} ;
end
else if (mode==1'b0)
begin
out <= {out[2:0],~out[3]};
end
  endmodule