Ring Counter ( Verilog ) with Test Fixture

Test Fixture Program :-
module tf_ring_vlog;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)
ring_vlog uut (
.out(out),
.clk(clk),
.reset(reset)
);

initial begin
clk=1'b1;
forever #5 clk=~clk;
end


initial begin
reset = 1;#10;
reset = 1;#10;
reset = 0;#30;

end
     
endmodule


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Program for Ring Counter (  VERILOG  ) :-

module ring_vlog(
 out      ,  // Output of the counter
 clk      ,  // clock input
 reset       // reset input
 );
 //----------Output Ports--------------
  output [3:0] out;
  //------------Input Ports--------------
  input clk, reset;
  //------------Internal Variables--------
  reg [3:0] out;
  //-------------Code Starts Here-------
  always @(posedge clk)
if (reset)
begin // active high reset
out <= 3'b0001 ;
end
else if (out==3'b0001)
begin
out <= 3'b0010;
end
else if (out==3'b0010)
begin
out <= 3'b0100;
end
else if (out==3'b0100)
begin
out <= 1000;
end
else
begin
out <= 2'b0001 ;
end

  endmodule